The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
In recent years, there has been increased use of an electronic circuit, such as, e.g., an LSI circuit (hereafter referred to as an “electronic circuit”) that includes a power backup capacitor. In such an electronic circuit, even if the power supply is interrupted due to, e.g., electric power failure, the electronic circuit can be continuously operated for a certain period of time using electric charges stored in the power backup capacitor. With this power backup capacitor, if the power failure continues only for a short period of time, for example, the data will not be cleared due to the power interruption. More specifically, in an electronic device having a timer recording function, the risk of occurrence of such inconvenience that the scheduled timer recording cannot be performed due to the power interruption can be reduced as low as possible.
Electric charges stored in a power backup capacitor will reduce with time, and therefore it is required to reset the electronic circuit before the backup voltage becomes lower than the operation lower limit voltage of the circuit to prevent a runaway thereof.
During the backup operation using the electric charges stored in the power backup capacitor, a predetermined voltage is generally used as a low reset voltage at which the circuit is reset when the backup voltage becomes lower than the predetermined voltage. When the power supply is resumed and then the backup voltage becomes higher than the reset voltage, the reset is terminated to resume the operation.
In a normal low voltage reset circuit, as shown in FIG. 4, when the voltage of the power backup capacitor becomes lower than a predetermined low reset voltage, a reset request signal is outputted, and when the voltage of the power backup capacitor becomes higher than the predetermined low reset voltage, the reset request signal is released. The reset state will be maintained when the voltage of the power backup capacitor is kept lower than the predetermined low reset voltage.
According to the aforementioned prior art, however, during the process in which the voltage of the power backup capacitor raises after resuming of the power supply, there is a risk that a malfunction may occur because of voltage fluctuates before restoration of the normal operation voltage after exceeding the predetermined reset voltage.
More specifically, for example, when power supplied from the main power source is interrupted for some reason, the electronic circuit enters into a backup state in which the circuit is operated by the electric charges stored in the power backup capacitor. The electric charges of the power backup capacitor gradually decrease with time, which in turn causes dropping of the voltage of the power backup capacitor. When the voltage reaches a predetermined voltage, the low voltage reset circuit resets the electronic circuit to prevent the possible malfunction. In order to secure the time from the interruption of the main power supply to the reset of the electronic circuit by detecting the low reset voltage as long as possible, it is required to make the low reset voltage as close to the operation lower limit voltage Vmin of the LSI as possible.
However, in cases where the low reset voltage is lowered too much, when the power supply is resumed and then the power supply voltage Vdd raises slightly, the reset state will be released. In this case, since the reset release timing is too early, the operation will be resumed at unstable voltages not sufficiently high. This may cause malfunction of the electronic circuit. To prevent such malfunction, if the low reset voltage is raised, the backup operation time becomes shorter.
Even in cases where a reset voltage can be set using a microcomputer in a programmable manner, it is hard to find the most suitable low reset voltage value.
Furthermore, in cases where a width of a conventional reset signal is increased using a counter, it is difficult to assuredly prevent the operation at unstable voltages while securing a sufficient time of the backup operation.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.